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GENLINXTM GS9001
EDH Coprocessor
DATA SHEET
FEATURES * Error Detection and Handling (EDH) according to SMPTE RP165 * EDH insertion and extraction in one device * autostandard operation DESCRIPTION The GS9001 implements error detection and handling (EDH) functions according to SMPTE RP165. Interfacing to the parallel port of either the GS9002/GS9022 serial digital encoders or GS9000 decoder, the GS9001 provides EDH insertion and extraction for 4sc NTSC, 4sc PAL and 4:2:2 component standards up to 18 MHz luminance sampling. The GS9001 also generates timing signals such as horizontal sync, vertical blanking, field ID and ancillary data identification. The ancillary data identification aids the extraction of ancillary data from the data stream.
* I2 C Serial communications interface for access to error flags and device configuration * available stand alone mode
* error flags available on dedicated outputs
* field, vertical, horizontal timing signals, ancillary data indication and TRS indication * video standard and invalid data indication * reserved words readable and writeable * 21 bit Errored Fields counter
* passthrough mode to bypass EDH packet insertion * true 8-bit compatibility
* 40 MHz operating frequency APPLICATIONS
* 4sc, 4:2:2 and 360 Mb/s serial digital interfaces * Source and destination equipment * Distribution equipment * Test equipment
Transmit/ Receive
D E DS NN EG M SI ME OD C EW RE TN OR NO F
The device has an I2C (Inter-Integrated Circuit) serial interface bus for communication with a microcontroller. The device can be programmed as an I2C slave transmitter or receiver by the microcontroller. This interface can be used to read the complete set of error flags and override the flag status prior to re-transmission. The device automatically determines the operating standard which can be overridden through the I2C interface. Timing signals and transmission error flags are also available on dedicated outputs. ORDERING INFORMATION
Part Number Package 44 PQFP Temperature GS9001-CQM OC to 70C
IC Interface
2
Device Address
Serial Clock & Data
Ancillary Check
Error Flags & Format
Transmission Error Flags
CRC Extraction
Compare
Interrupt
Automatic Standards Detection
Control Logic
Errored Field Counter
Mux
Data Out
Data In Clock Reset
Field Signals/ Standard Indication
CRC Calculation
HSync, VBlank, Ancillary Data, TRS-ID, TRS Absence Indication
I2C is a registered Trademark of Philips
Revision Date: February 2001
BLOCK DIAGRAM
Document No. 521 - 38 - 03
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905 632-2996 fax: (905) 632-5946
Gennum Japan Corporation: A-302, Miyamae Village, 2-10-42 Miyamae, Suginami-ku,Tokyo 168, Japan tel. (03) 3334-7700 fax (03) 3247-8839
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (V =VDD-V ) s ss Input Voltage Range (any input) DC Input Current (any one input) Power Dissipation Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10 seconds) VALUE/UNITS 7V -0.3 to (VDD+0.3) V 10 A 800 mW 0C to 70C -65C to +150C 260C
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
ELECTRICAL CHARACTERISTICS Parameter
Supply Voltage Supply Current
TTL Compatible CMOS Inputs
Input Leakage
TTL Compatible CMOS Outputs
AC Parameters @ VDD = 5V, VSS = 0V, TA = 0oC - 70oC unless otherwise shown Parameter Symbol Conditions
Input Clock Frequency
Input & Output Data Rates Input Data & Clock Rise Time
Setup Time Hold Time
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DC Parameters @ VDD = 5V, VSS = 0V, TA = 0oC - 70oC unless otherwise shown Conditions Min Typ Max Symbol VS IS Units V Operating range 4.75 5.00 85 5.25 100 Operating range TA=25oC TA=25oC mA VIHmin 2.00 V V VILmax IIN 0.80 VIN=VDD or VSS TA=25oC TA=25oC TA=25oC TA=25oC 10 A VOHmin 2.40 4.50 V VOLmax IOL 0.20 0.40 -4 4 V mA IOH mA Min Typ Max Units clk 40 MHz data 40 Mb/s tir 1 ns tset TA=25oC 2 ns thold tP tor SCL CL < 30pF TA=25oC 2 3 2 5.5 3 100 8.5(1) 4 400(2) ns ns ns kHz
Input Clock to Output data Output data rise/fall time SCL Clock Frequency
(1) (2)
TA = 70c, VDD = 4.75V Determined by I2C bus specification 2
521 - 38 - 03
F2/NTSC_PAL
F1/D1_D2
VBLANK
ANC_DATA
F0/HD1
44 (MSB) DIN9 1
43
42
41
40
39
38
37
HSYNC
FL0
FL1
36
35
NO TRS
VDD
VSS
34 33
DOUT9 (MSB)
DIN8 DIN7 DIN6 DIN5
2
32
DOUT8 DOUT7 DOUT6 DOUT5
3
31
4
30
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5 29 DIN4 6
GS9001 TOP VIEW
28
DOUT4
DIN3
7
27
DOUT3
DIN2
8
26
DOUT2
DIN1
9
25
DOUT1
(LSB) DIN0
10
24
DOUT0 (LSB)
CLK
11
23
INTERRUPT
12
13
14
15
16
17
18
19
20
21
22
FIELD/STD
RSTN
VDD
SCL
S1
Fig. 1 GS9001 EDH Coprocessor Pin Connections
Table 1. Selection of Field and Video standard signals on F2, F1, F0 pins Output F2 Output F1
Input Field/Std 0
SDA
R/T
S0
A0
VSS
A1
Output F0
NTSC (0) / PAL (1) Field Bit 2
D1 (0) / D2 (1)* Field Bit 1
13.5 MHz Y (0) / 18 MHz Y (1) Field Bit 0
1
*D1: 4:2:2
D2: 4
sc
sampling sampling
Table 2. Selection of Error status flags to display Input S0 0 Output FL1
Input S1 0
Output FL0
EDA Full Field
EDH Full Field
0 1 1
1 0 1
UES (See Note) EDA Ancillary IDA (See Note)
EDH Active Picture EDH Ancillary IDH (See Note)
NOTE:
The UES, IDH and IDA flags that appear on pins FL0 and FL1 as shown in Table 2, represent the sum of each corresponding flag for active picture, full field and ancillary. UES indication can also be used to identify the absence of EDH implementation in the upstream equipment.
3
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GS9001 PIN DESCRIPTIONS PIN NO. 1-10 11 12 SYMBOL DIN[9..0] CLK R/T TYPE I I I DESCRIPTION Parallel digital video data inputs Parallel clock input. Receive or Transmit mode select. High - CRC extraction, recalculation, comparison, error indication, re-insertion. Low - CRC calculation, insertion, clears error flags 13 FIELD/STD I Field or Standard indication select. High - Field signals on F0, F1, F2. Low - Standard indication on F0, F1,F2. (Refer to Table 1) 14,15 16 S0, S1 RSTN I I Error flag select inputs. Select type of error flag to output on FL0, FL1. (Refer to Table 2) Master Reset. Active low input, which provides option to initialise internal circuitry. The GS9001 contains power on reset circuitry that automatically initialises all internal states including the I2C Interface.
2
19,20 21
22 23
24-33 34
35
36
37 40-42
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A0,A1 SCL I Device address select pins for I C interface bus. (Refer to Table 3) I Serial Clock for I2C Interface bus. SCL and SDA must be connected to GND if there is no I2C interface connected to the device. SDA I/O O Serial Data for I2C Interface bus. INTERRUPT Programmable interrupt for error flag indication. Active low, open drain output. Interrupt can be made sensitive to specific or all error flags (described in I2C WRITE format section). Default is sensitive to all error flags. This output stays active until a word is read from the device. DOUT[0..9] O Parallel digital video data outputs NO TRS O Indicates presence of invalid input data, containing no timing reference signal (TRS). Active high output which signals absence of seven consecutive valid TRSs in the incoming data. Returns to low state after seven consecutive valid TRSs occur. A valid input CLK must be present for this to operate. ANC DATA O Ancillary data presence indication. Active high output, indicates data presence from ANC data header word to checksum word. Can be programmed through the I2C interface to also indicate presence of TRS-ID (3FF,000,000) blocks. In this mode, output stays high for 5 words during composite video TRS-ID and 4 words during component EAV, SAV. In stand alone operation mode without I2C Interface, this feature can be forced on ANC DATA pin by selecting address 0,1 on A1,A0 pins. (NOTE: SCL and SDA must be connected to GND when I2C Interface is not used) HSYNC O Horizontal sync indication. Active high, extends from EAV to SAV for component video, indicates TRS-ID location for composite video. V BLANK F0/HD1 F1/D1_D2, F2/NTSC_PAL O Vertical blanking interval indication. Active high during this period. O Field or standard indication pins. Field signals output when FIELD/STD pin is high, Video standard when FIELD/STD is low. FL1,FL0 O Error Flag Status. Active high outputs programmed via S0, S1 to indicate various transmission and hardware related error flags. Output flags stay active for one field. VDD VSS P P Power Supply. Most positive power supply connection. (+5V) Power Supply. Most negative power supply connection. (GND)
43,44
17,39 18,38
521 - 38 - 03
4
GS9001 - DETAILED DEVICE DESCRIPTION. The GS9001 contains all functional blocks required to implement Error Detection and Handling according to SMPTE RP165. It also provides Field, Vertical, and Horizontal timing information as well as Ancillary Data and TRS-ID indication. The device offers standard independent operation and an I2C serial communications interface to allow reading/writing of error flags, device configuration and video standards format. The device can also be operated in stand alone mode without the I2C interface with error flags available on dedicated output pins. In all modes, the device latency is four clock cycles. Automatic Standards Detection The presence of ancillary data is indicated by a logic high that extends from the Data ID word to the Checksum word of each ancillary packet. These timing signals are available on dedicated output pins and through the I2C communications interface. The control logic also verifies incoming data validity by checking the occurrence of consecutive TRS-IDs. If the absence of seven consecutive TRS-IDs is detected, a "NO TRS" flag is output on pin 34. This flag is reset once seven consecutive TRS-IDs occur. CRC Calculation
This block analyses the incoming 8 or 10 bit data to determine whether it is component or composite. In total, six standards are automatically detected. For composite data conforming to SMPTE 259M, the Timing Reference Signal and Identification (TRS-ID) packet contains line and field information used to detect the format. For component data conforming to SMPTE 125M, the TRS-ID packets for End of Active Video (EAV)and Start of Active Video (SAV) are used to determine the format. The TRS information is then used to determine whether the composite signal is NTSC or PAL, or whether the component signal has 13.5 MHz or 18 MHz luminance samples.
Noise immunity has also been included, to ensure that momentary signal interruption does not affect the autostandards detection function. This built in noise immunity results in delayed switching time between standards. Delays range from as little as eight lines when switching between component standards to as much as four frames when switching between PAL and NTSC composite standards. The latter delay is due to the method used to differentiate PAL and NTSC, which counts the number of lines per frame and requires four sequential frames before switching standards. Manual override of the auto-standard feature is provided via the I2C interface, for applications where the standards recognition delay is intolerable. Standards indication is provided on multiplexed output pins or via the I2C interface. Control Logic
The control logic coordinates operation and extracts timing signals such as vertical blanking, horizontal sync, field ID, ancillary data indication and TRS-ID indication.
The vertical blanking interval signal is active during the digital vertical blanking period for all signal formats. The horizontal sync signal is provided as a pulse with a duration of one clock period for every TRS-ID occurrence in composite video. For component video, the horizontal sync is a positive going pulse which starts at EAV and ends at SAV. Three field ID bits (pins 40, 41, 42) indicate the two fields for component video standards, the four colour fields for composite NTSC or eight colour fields for composite PAL. The ancillary data indication allows external circuitry to identify ancillary data in the data stream for extraction or masking.
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A cyclic redundancy check (CRC) is calculated for each video field according to the CRC-CCITT polynomial X16+X12+X5+1. Separate CRCs are calculated for active picture and full field to provide an indication that active video is still intact despite possible full field errors. This allows the user to distinguish between different classes of data errors, which yields the best compromise in error detection for all types of equipment. In order to provide compatibility between 8 bit and 10 bit systems, all data words with values between 3FCH and 3FFH inclusive, are recoded as 3FFH at the input of the polynomial generator. Start and end points for the CRC calculation are as defined in RP165 and depend on the standard and check field being calculated. Calculated CRC words can be read through the I2C interface. CRC Comparison The GS9001 can be configured for transmit or receive mode. In receive mode, the calculated CRC is checked against the incoming CRC embedded in the error data packet. Any mismatch will generate status error flags to indicate transmission related error flags in either active picture, full field or both. The error flags resulting from CRC mismatch are full field error detected here (EDH) and active picture EDH. Ancillary Checksum Verification The ancillary data checksums are also verified to ensure data integrity. Ancillary data is preceded by the Data Header, Data ID, Block Number and Data Count. The Data Count shows the number of ancillary words contained in each ancillary data packet. A checksum is calculated for each incoming ancillary data packet and compared with the transmitted checksum. Any difference is reported as an error via the ancillary EDH error flag. A separate ANC EXT error flag is also provided to indicate corruption of the EDH data packet. Error Flags and Formatting This block performs the functions of error flag reporting and recoding, EDH data packet construction, programmable interrupt generation and interface with the I2C communication block.
5
521 - 38 - 03
Error Reporting Error reporting is meant to provide the information necessary to allow system diagnostics. There are fifteen error flags in total, which are used to identify specific error types. All flags are available to be read or overwritten via the I2C interface. The definition of these flags and an explanation of how the device handles these flags are described below. The acronyms used are: 7.
UES for AP, FF and Ancillary U E S i s s e t i f t h e i n c o m i n g U E S i s s e t . A l s o, i f t h e incoming data does not have an error data packet, this flag is set. This is to inform the downstream devices that the data being sent has not been previously checked for data errors.
EDA EDH IDH IDA
Error Detected Already Error Detected Here Internal device error Detected Here
UES AP FF
1.
EDH for AP and FF
If the incoming CRC checkword is different from the calculated CRC checkword, the EDH flag is set. 2.
EDH for Ancillary
If the checksum for the ancillary data does not match the calculated checksum, this flag is set. 3.
EDA for AP and FF
This flag is generated by summing the incoming EDA flag with the product of the incoming EDH f l a g a n d t h e v a l i d C R C b i t . A s a result, if the incoming EDH flag is set and the EDA flag has not been set, the EDH flag will be recoded to EDA and then cleared. If the incoming CRC is invalid, then the outgoing EDA flag will be determined by the incoming EDA flag only. This is to support devices in the transmission path that do not generate valid CRC,yet pass only the EDA flags. 4.
EDA for Ancillary
This flag is the sum of the in-coming EDH and EDA flags for ancillary data. 5.
IDH for AP, FF and Ancillary
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These flags are available for applications where access to the Internal device error Detected Already Unknown Error Status Active Picture Full Field I2C interface via microcontroller is not possible or cost effective. These flags give the user immediate warning of transmission related errors either locally or from upstream equipment. In situations where the upstream equipment does not support EDH, a new error data packet is inserted in the data stream as specified in RP165. In this case the UES flag is set for active picture, full field and ancillary data. The EDH, EDA and IDA flags are reset for active picture and full field. For ancillary data, the EDH flag is still reported if there are any checksum errors and the EDA and IDA flags are reset. This is done since the checksums for ancillary data may still be valid without the presence of an error data packet in the data stream. Transmit vs Receive Modes The preceding description refers to the device in Receive mode. In Transmit mode, valid CRC-check words for active picture and full field are inserted and all error flags are reset. Flag Masking Any of the fifteen error flags can be set/reset or made transparent using the I2C interface. Transparent flags are updated on the occurrence of data errors. Flag masking can be done only when the device is in the receive mode. During transmit mode all error flags are reset. The transmit mode would be used for source equipment and equipment that modifies or processes the data before re-serializing. Programmable Interrupt The interrupt output can be made sensitive to any specific or all error flags. This function is programmed using the sensitivity flags SANC, SFF and SAP as described in the section for I2C interface WRITE format. Errored Field Counter This 21 bit counter can be used to count the number of fields in which data errors occur. The same set of sensitivity flags used for the programmable interrupt, also control the incrementing of this counter. This counter can be made to increment on the occurrence of any specific type of error flag in a field. 6
In addition to error flag access through the I2C interface, selected EDH, EDA, IDH, IDA and UES flags are available on two user programmable output pins. Table 2 (on page 3) shows these error flags and the corresponding input addresses.
These flags are set by the user through the I 2 C serial interface. They can be used to indicate any internal device errors in the vicinity of the device. Examples could be local hardware errors such as a RAM failure or a system diagnostics failure on powerup. 6.
IDA for AP, FF and Ancillary
This flag is the sum of the incoming IDH and IDA flags for AP, FF and ancillary data.
521 - 38 - 03
The counter can be programmed either to clear automatically when the counter status is read via the interface, or to clear when forced through the interface. I2C Serial Communications Interface The serial communications interface allows access to all error flags and other internal programmable functions. The InterIntegrated Circuit (I2C) protocol is used. For information on the GS9001 I2C protocol, refer to Document 521 - 59 "Using the GS9001 EDH Coprocessor". The slave addresses for the I2C interface are given in Table 3. Data formats for the I2C interface READ and WRITE operations are given in Tables 4 and 5.
During the stand-alone mode of operation, flag masking, video standard override and programmable interrupt features are disabled. The user can still monitor the video standard and the error flags through dedicated pins as shown in Table 2. EDH Passthrough Mode An EDH passthrough mode is available to aid in system diagnostics. This mode is selected by address 1,0 on A1, A0 pins. In this mode, the GS9001 will not insert a new EDH packet into the data stream. Input data is bypassed to output without modification. Error flag status available through the I2C interface and output pins, is now invalid. However, valid CRC words can be read through the I2C interface every field, for a static picture.
NOTE:
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Table 3. I2C Slave Addresses I2C Address is 00011A1 A0 A0 0 1 0 1 A1 0 0 1 1 Function Available Device Address Available Device Address EDH Passthrough Mode Test Mode If an I2C interface is not used, address 0, 1 will force TRS-ID indication on the ancillary data pin. This is to facilitate applications in which TRS-ID is desired, but an I2C interface is not used. In this case, the SCL clock line must be connected to the most negative supply.
7
521 - 38 - 03
Table 4. I2C - Interface: Data Format for READ 15 Words
Word Address 1 Databits B4 B3 ANC UES FF IDH ANC IDA FF EDA Comments B2 ANC IDH FF EDH NTSC PAL B1 ANC EDA AP UES HD1 D1 B0 ANC EDH AP IDA D1 D2 Video standard & error counter 15 Error Flags (according to SMPTE RP165) see note below for flag ANC EXT
B7 AP IDH ANC EXT
B6 AP EDA FF UES
B5 AP EDH FF IDA
2
3 b20
4
5
6
7
8
9
10
11
12
13
14
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b15 b14 b13 Error counter b12 b11 Error counter b4 b3 Error counter 21 bits wide b10 b9 b8 b7 b6 b5 b2 b1 b0 b15 b14 b13 Active Picture CRC b12 b11 b10 Active Picture CRC b4 b3 b2 Full Field CRC b12 b11 b9 b8 Active picture CRC 16 bits wide b7 b6 b5 b1 b0 Full Field CRC 16 bits wide b15 b14 b13 b10 b9 b8 b7 b6 b5 Full Field CRC b4 b3 RW1 b5 b2 b1 b0 RW2 b3 RW2 b2 RW1 b7 RW1 b6 RW1 b4 RW1 b3 RW1 b2 Bits 2 to 7 for reserved words 1 to 7 RW3 b5 RW3 b4 RW3 b3 RW3 b2 RW4 b4 RW2 b7 RW4 b3 RW2 b6 RW4 b2 RW2 b5 RW3 b7 RW2 b4 RW3 b6 RW4 b7 RW4 b6 RW4 b5 Example: Bit number 4 of reserved word 2 is denoted as RW2 b4 RW6 b3 RW7 b5 0 RW6 b2 RW7 b4 0 RW5 b7 RW7 b3 0 RW5 b6 RW7 b2 0 RW5 b5 RW6 b7 0 RW5 b4 RW6 b6 0 RW5 b3 RW6 b5 RW5 b2 RW6 b4 RW7 b7 RW7 b6 Reserved Words 1 to 7 in an EDH packet are both readable and writable. Only bits 2 to 7 of each reserved word are available. During Write operation for every reserved word, Even Parity is added as bit 8 and bit 9 is the logical inverse of bit 8. Bits 0 and 1 are zero to maintain compatibility with 8 bit systems. 16 bit Active Picture CRC and Full Field CRC words are available for every field, through the I2C interface.
Error counter b19 b18
b17
b16
15
NOTES: The error counter is 21 bits wide and counts the number of fields that had errors. This counter can be made to increment only upon the occurrence of a specific type of flag in a field. This sensitivity is programmable through SANC,SFF & SAP class of flags (see WRITE section). ANC EXT is a flag defined to indicate any checksum error in the EDH packet.
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8
Table 5.
Word Address 1
I2C - Interface: Data Format for WRITE 12 Words
B7 AP IDH STICKY FLAGS MAP IDH B6 AP EDA FF UES MAP EDA MFF UES B5 AP EDH FF IDA MAP EDH MFF IDA Databits B4 B3 ANC UES FF IDH MANC UES MFF IDH ANC IDA FF EDA MANC IDA MFF EDA Comments B2 ANC IDH FF EDH MANC IDH MFF EDH B1 ANC EDA AP UES MANC EDA MAP UES B0 ANC EDH AP IDA MANC EDH MAP IDA Mask Status for the 15 Error Flags (see Note 1) 15 Error Flags (according to SMPTE RPI65)
2
3
4
5
6
7
8
9
10
11
12
NOTES: 1. Mask status is used for flag masking. MASK RW is 1 to overwrite Reserved Words. Bit STICKY FLAGS will make the flags sticky. (Flag stays set until read by I2C interface) 2. Sensitivity status defines the interrupt & error counter sensitivity. Please note for UES flag sensitivity, there is only one bit which is the SALL UES bit. This covers the UES bit for Ancillary, Active Picture and Full Field classes. 3. Bit SEL STD: 1 to overwrite video standard, 0 for auto standard selection Bit NTSC/PAL: 1 for PAL (625/50) standard, 0 for NTSC (525/60) standard Bit HD1/D1: 1 for Component 4:2:2 standard with 18Mhz Luminance, 0 for Component 4:2:2 standard with 13.5 MHz Luminance Bit D1/D2: 1 for 4sc composite standard, 0 for Component 4:2:2 standard Bit TRS SEL: 1 to force TRS-ID indication in addition to ancillary data indication on the Ancillary Data pin, (pin 35) 0 to force only ancillary indication on the ancillary data pin (pin 35) Bit CLR CNT: 1 to clear the `errored field counter'. 0 to let the counter count the errored fields Bit AUTO CLR: 1 to automatically clear the `errored field counter' after every reading of the counter status through the interface, 0 to disable this automatic clear feature Default Status: On power-up all bits are set to zero except for the sensitivity flags which are set to one. Stand-Alone Operation: All bits will stay at power-up initial conditions, as described above, when there is no interface connected to the device, except for the bit TRS-SEL, which can be set to one by connecting the A1and A0 pins to 0,1 respectively.
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MASK RW SAP IDH SAP EDA SAP EDH TRS SEL SALL UES SFF IDA SANC IDA SFF IDH SANC IDH SFF EDA SANC EDA SANC EDH Sensitivity Status for the15 Error Flags (see Note 2) AUTO CLR CLR CNT SFF EDH SAP IDA RW1 b3 RW1 b2 0 0 SEL STD NTSC PAL RW1 b6 HD1 D1 D1 D2 Standard Select (see Note 3) RW2 b5 RW2 b4 RW2 b3 RW2 b2 RW1 b7 RW1 b5 RW1 b4 RW3 b7 RW3 b6 RW3 b5 RW3 b4 RW3 b3 RW3 b2 RW2 b7 RW2 b6 Bits 2 to 7 for reserved words 1 to 7 Example: Bit number 4 of reserved word 2 is denoted as RW2 b4 RW5 b3 RW6 b5 RW7 b7 RW5 b2 RW6 b4 RW7 b6 RW4 b7 RW6 b3 RW7 b5 RW4 b6 RW6 b2 RW7 b4 RW4 b5 RW5 b7 RW7 b3 RW4 b4 RW5 b6 RW7 b2 RW4 b3 RW5 b5 RW6 b7 RW4 b2 RW5 b4 RW6 b6
9
521 - 38 - 03
Reset and Interrupt Characteristics (VCC = 5V, 0C < TA < 70C) PARAMETER Minimum Rest Pulse Duration External to Internal Reset Delay SYMBOL tr(min) trd1 trd2 Interrupt Delay after RSTN tid MIN 100 MAX 12 3 12 UNITS nS nS S nS
INTERRUPT
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VDD
Vt TRIGGER
INTERNAL RESET
RSTN
Fig. 2a GS9001 Internal Reset Circuit
trmin
RSTN
INTERNAL RESET
trd1
trd2
INTERRUPT
tid
Fig. 2b Reset and Interrupt Timing
Active Low
Line 11/272 - Sample 1456 - NTSC (525/60) 4:2:2 Line 11/272 - Sample 1936 - NTSC (525/60) 4:2:2,16 x 9 Line 11/272 - Sample 806 - NTSC (525/60) 4sc Line 7/320 - Sample 1456 - PAL (625/50) 4:2:2 Line 7/320 - Sample 1936 - PAL (625/50) 4:2:2,16 x 9 Line 7/320 - Sample 983 - PAL (625/50) 4sc
I2C READ AFTER SECOND WORD (Interrrupt is inactive after second word of the I2C packet is read)
Fig. 2c Interrupt Timing
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10
EDH PACKET
DATA COUNT (110)
DATA ID (1F4)
B. N. (200)
DATA HEADER
DATA HEADER
DATA HEADER
CHECK SUM
RES WORD
RES WORD
RES WORD
RES WORD
RES WORD
RES WORD
ANC ERROR
RES WORD
AP ERROR
FF ERROR
AP CRC
AP CRC
AP CRC
FF CRC
FF CRC
FF CRC
XXX
XXX
OUTPUT DATA STREAM WITH EDH PACKET ANCILLARY ERROR FLAGS ACTIVE PICTURE ERROR FLAGS FULL FIELD ERROR FLAGS
X DON'T CARE
XXX
XXX
XXX
D E DS NN EG M SI ME OD C EW RE TN OR NO F
X X X X X X
Fig. 3 Error Flag Timing
CLOCK
000H
3FFH
2FEH
202H
200H
100H
XXX
XXX
3FFH
000H
200H
XXX
XXX
XXX
XXX
DATA IN
XXX
XXX
000H
3FFH
2FEH
202H
200H
100H
XXX
XXX
3FFH
000H
200H
XXX
XXX
DATA OUT
ANC_DATA
ANCILLARY_DATA
TRS_DATA
(IF TRS INDICATION IS ENABLED)
Fig. 4 Ancillary Data Indication Timing
CLOCK
3FFH
000H
EAV
XXX
XXX
3FFH
000H
SAV
XXX
XXX
DATA IN
XXX
3FFH
000H
EAV
XXX
XXX
3FFH
000H
SAV
XXX
XXX
DATA OUT
HSYNC
X
X
VBLANK
X X DON'T CARE
X
FIELD
Fig. 5 Component Timing Signals
11
521 - 38 - 03
CLOCK
XXX
3FFH
000H
TRS-ID
XXX
XXX
XXX
DATA IN
XXX
3FFH
000H
TRS-ID
XXX
DATA OUT
HSYNC
VBLANK
10 BIT PARALLEL INPUT PCLK INPUT
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Fig. 6 Composite Timing Signals
XXX
XXX
FIELD
Line 525 Line 263 Line 623 Line 310 Note:
Sample 765 Sample 310 Sample 379 Sample 945
(525/60) Odd Fields (525/60) Even Fields
Line 9 Sample 764 Line 272 Sample 764
(625/50) Odd Fields (625/50) Even Fields
Line 5 Sample 944 Line 317 Sample 944
All sample numbers are with respect to output data.
Fig. 7 Composite VBLANK Timing
USER SET
STATUS FLAGS
F, V, H
ERROR FLAGS
TIMING
CO-AXIAL CABLE
EDH
SERIALIZER
CABLE DRIVER
RECEIVER/
DESERIALIZER
EDH
10 BIT PARALLEL DATA
PCLK
Fig. 8 GS9001 System Placement
APPLICATIONS The GS9001 can be used on either the transmit or receive side of the serial digital interface. As shown in Figure 8, it is used as the last stage prior to serialization and immediately after deserialization. The nature of the EDH error flags and the flexibility of use with an I2C interface or in stand alone operation, make the GS9001 suitable for most system applications.
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Conformance to SMPTE standards for EDH and digital video, ensures compatibility with any piece of source, destination or routing equipment. Complete, System-Wide Implementation of EDH Figure 9 shows a typical system implementation using EDH , where both equipment fault errors and transmission errors occur.
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These errors result in the transmission error flags EDH and EDA and the non-transmission related flags IDH and IDA. In Figure 9, the AES/EBU audio encoder has generated an error during the audio formatting process and reported an IDH (Internal device error Detected Here) error. The signal from the audio encoder then experiences degradation from a faulty cable, before it reaches the router. In this case, the cable is marginal and is producing random infrequent errors. A GS9001 device in the router flags these errors as EDH (Error Detected Here) for Active Picture, Full Field or both. Incoming IDH flags are also recoded as IDA (Internal device error Detected Already).
The next device in the chain is a distribution amplifier (DA) which is receiving its input from the router. The GS9001 device in the DA will recode the incoming EDH flag as EDA (Error Detected Already) and pass the IDA flag. An additional transmission error occurs between the DA and the production switcher which is flagged as EDH. The GS9001 in the production switcher now has a list of error flags that can be reported locally or through a communications interface to a central maintenance station.
D E DS NN EG M SI ME OD C EW RE TN OR NO F
VTR
Video IDH EDH IDA Transmission Error Audio
AUDIO ENCODE
ROUTER
DA
Internal Device Error
Transmission Error
EDA IDA
Communication
Interface
CENTRAL MICROPROCESSOR
PRODUCTION SWITCHER
EDH EDA IDA
Fig. 9
VTR
(NO EDH)
Video
UES IDH
UES IDH
Transmission Error
Audio
AUDIO ENCODE
ROUTER
(NO EDH)
DA
Internal Device Error
Transmission Error
UES IDA EDH
Communication
Interface
CENTRAL MICROPROCESSOR
PRODUCTION SWITCHER
UES IDA EDA EDH
Fig. 10
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Partial EDH System Implementation In real system implementations not all equipment will have EDH capability. EDH is still useful in this environment. Figure 10 shows the same system implementation as Figure 9 except the VTR and router do not have EDH capability. With reference to Figure 10, the audio encoder will detect the lack of imbedded EDH in the incoming video, create the EDH Packet and assert the UES (Unknown Error Status) flag.The system will now have EDH monitoring for all downstream transmission and equipment errors. The router, without EDH, will simply pass the EDH packet unmodified to the DA which has EDH capability. Any errors reported at the DA could have occurred: 1. 2. 3. If the modifying equipment employs EDH on the output, a new CRC will be calculated and inserted. If, however, the equipment has no EDH capability, the original CRC would be passed through. This would result in incorrect CRC comparison and erroneous error flag generation by the next piece of equipment. This problem can be mitigated if the downstream equipment has the ability to override specific error flags. Unfortunately, there is no way for the downstream equipment to determine if errors were caused by data modification or transmission errors. It is therefore important that the equipment which modified the video data either implement EDH properly or remove the full field EDH packets from the data stream. Removing these packets will cause the UES flag to be asserted but this is preferable to reporting false errors. As shown in Figure 11, the preferred way to implement EDH in equipment which modifies the data is to have an EDH coprocessor at both the input and output. The input EDH coprocessor validates the integrity of the input data. The output EDH coprocessor, set to receive mode, will pass any error flags that may have been generated upstream and recalculate any CRCs that need to be changed due to data modification. Flag masking is then enabled in this output EDH coprocessor to avoid flagging an erroneous full field error due to CRC mismatch in the modified data.
on the link between the audio encoder and the router, in the router, or
on the link from the router to the DA.
Although this does not provide ideal coverage, the source of errors can still be isolated to allow the required maintenance. Data Modification and EDH
It is often necessary to modify the data stream after the initial generation of the CRC words. This would occur in applications such as vertical interval timecode (VITC) or audio insertion.
References:
1. Singar Bala, Eric Fankhauser and Paul Moore,
An IC Implementation of SMPTE RP165: Error Detection and Handling, SMPTE Journal, Volume 104, Number 7, July 1995, pp 459 - 464.
D E DS NN EG M SI ME OD C EW RE TN OR NO F
VIDEO SOURCE
EDH
ANCILLARY INSERT e.g. VITC
EDH
MODIFIED VIDEO DATA
MICROPROCESSOR
Fig. 11
DOCUMENT IDENTIFICATION
PRODUCT PROPOSAL This data has been compiled for market investigation purposes only, and does not constitute an offer for sale. ADVANCE INFORMATION NOTE The product is in a development phase and specifications are subject to change without notice. Gennum reserves the right to remove the product at any time. Listing the product does not constitute an offer for sale PRELIMINARY The product is in a preproduction phase and specifications are subject to change without notice.
REVISION NOTES
Watermark added.
For latest product information, visit www.gennum.com
DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright June 1995 Gennum Corporation. All rights reserved. Printed in Canada.
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